Hi,
| I have an urgent requirement with one of my clients, details given below. If you find yourself suitable for the position, please send me your latest updated resume along with contact details. Please include your employer details as well. |
3 positions
1) ASIC FE Verification,
2) ASIC FE Implementation,
3) MASK design
Rate : $45/hr
Long Term
MOI -Skype
Location – Folsom, CA
Look for candidates who are willing to relocate within west coast. Thanks.
1) Location – Folsom, CA
ASIC FE Verification
| Must Have Skills | Desirable Skills | Role description |
| 5+ years of industry experience in ASIC RTL verification using System Verilog & UVM methodology. | Proficiency in C, C++, Perl / TCL | To build verification Environment for a complex SoC from scratch using System Verilog / UVM methodology |
| Experience in bus protocol AMBA AHB / AXI. | Expertise in Protocols like USB, PCIe, DDR | To develop Test plan, write test cases & Debug. |
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| Functional Verification and GLS |
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| Signoff using Functional coverage metrics. |
2) ASIC FE Implementation
Folsom, CA
| Must Have Skills | Good To have: | Role description: |
| · Developing constraints, Static timing analysis (STA) and timing closure at the chip level – Synopsys Primetime | · CDC checking using tools such as Spyglass, 0in | · Chip level static timing analysis and timing closure |
| · Synthesis of high speed, large gate count designs using Synopsys Design Compiler, or RTL Compiler | · Lint checking with Spyglass or other industry standard tools | · Understand design constraints, develop scripts for synthesis and formal equivalence and close pre-layout design timing |
| Formal verification with tools such as Conformal, Formality or other industry standard tool | · Scripting in Perl/Shell and Tcl | · Synthesis and LEC of large gate count, high speed blocks |
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| · Good Communication and Interpersonal Skills |
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3) MASK design
Folsom, CA
| Must Have Skills | Good To have: | Job Responsibility: |
| At least 4 – 8 years experience in understanding and Independent handling of various Analog and Mixed Signal blocks such as LDO, Switching Regulators, Data Converters, PLL, SerDes, LVDS and top level layout integration of AMS blocks. | Knowledge of scripting languages such as Perl/Tcl and Skill is a plus. | - Layout design, Verification, Post-layout fixes and sign-off of high performance of Analog and Mixed Signal blocks, and IO / High Speed IO blocks |
| Good Understanding of deep sub-micron layout techniques and issues in CMOS process technology nodes like 14nm,22nm, 16nm FinFET technologies | Full-chip integration and verification experience | - Mask Design team lead for the client engagement |
| Experience in Genesys / Genoa layout editor, Aapr flow, Helix etc | Good team player with excellent communication skills, interfacing with the circuit team | - Interface with the Circuit Design team at Onsite |
| Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc. |
| |
| Deep understanding of reliability analysis in layout like EM, IR drop, latch-up, ESD etc using Apache tools |
| |
| Should have good knowledge of CMOS, FinFET process and fabrication |
| |
| Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC) , Hercules |
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"Action is the foundational key to all success"
Thanks & Regards,
Dheeraj Chauhan
Technical Resource Specialist
| Zodiac Solution Inc. |
| Phone : 484-436-4300 |
| Email : dheeraj@zodiac-solutions.com |
| URL : www.zodiac-solutions.com |
G talk/hangout : dheeraj.rgtalent@gmail.com
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