Urgent requirement :: VLSI / System Verilog @ CA

Role :  VLSI / System Verilog
Experience Level :   5-8YEAR
Location : San Jose,  CA
Duration : 6+ months

Job Description:
•    Experience in pre-silicon verification.
•    Expertise in Building scalable HVL based verification environment from Scratch using System Verilog OVM/UVMc.
•    Good experience in System Verilog.
•    OVM/UVM based verification environment developmentd.
•    Sound understanding of Random and constrained random-verification conceptse.
•    Experience with assertion based verification would be a plusf.
•    Understanding  PCI-E, USB, SATA, DDR3  type protocols would be a plus.
•    Driving the verification environment architecture.
•    Creating test scenarios(System Verilog OVM)c. Work with RTL teams to debug verification failures. Review and ensure that expected Code and functional coverage metrics are achieved.


Thanks & Regards
Tirth Patel
Technical Resource Specialist
SysMind LLC
Desk: 609-897-9670 *2181
Email: tpatel[at]sysmind.com
In case I am not available please call Anoop: 609-297-0796
 
 
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